View PL680-37_323234.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
FEATURES
* * * Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies. Less than 25ps peak to peak jitter for all frequencies. Low phase noise output (@ 1MHz frequency offset -144dBc/Hz for 106.25MHz -144dBc/Hz for 156.25MHz -144dBc/Hz for 212.5MHz -140dBc/Hz for 312.5MHz, -131dBC/Hz for 622.08MHz 19MHz-40MHz crystal input. 38MHz-640MHz output. Available in PECL, LVDS, or CMOS outputs. Output Enable selector. 2.5V & 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages.
PACKAGE PIN ASSIGNMENT
VDDANA XIN XOUT SEL2^ OE_CTRL DNC GNDANA LP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GNDBUF QBAR VDDBUF Q GNDBUF LM
PL680-3X
* * * * * *
16-pin TSSOP
VDDANA
SEL0^
10
XOUT SEL2^ OE_CTRL DNC
12 13 14 15 16 1
11
SEL1^
9
XIN
8 7 6
GNDBUF QBAR VDDBUF Q
DESCRIPTION
The PL680-3X is a monolithic low jitter and low phase noise high performance clock, capable of maintaining 0.4ps RMS phase jitter and CMOS, LVDS or PECL outputs, covering a wide frequency output range up to 640MHz. It allows high performance and high frequency output, using a low cost fundamental crystal of between 19-40MHz.. The frequency selector pads of PL680-3X enable output frequencies of (2, 4, 8, or 16) * F XIN . The PL680-3X is designed to address the demanding requirements of high performance applications such Fiber Channel, serial ATA, Ethernet, SAN, etc.
PL680-3X
2 3 4
5
GNDANA
3x3 QFN
Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCO Divider Charge Pump + Loop Filter Output Divider (1,2,4,8)
GNDBUF
LP
LM
XIN XOUT
XTAL OSC
Phase Detector
VCO (F XiN x16)
QBAR Q
Performance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
OUTPUT ENABLE LOGICAL LEVELS
Part #
PL680-38 (PECL) PL680-37 & 39 (CMOS or LVDS)
OE
0 (Default) 1 0 1 (Default)
State
Output enabled Tri-state Tri-state Output enabled
PIN DESCRIPTIONS
Name
VDDANA XIN XOUT SEL2 OE_CTRL DNC GNDANA LP LM GNDBUF Q VDDBUF QBAR GNDBUF SEL1 SEL0
TSSOP Pin number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3x3mm QFN Pin number
11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10
Type
P I O I I P P O P O P I I VDD for analog Circuitry.
Description
Crystal input pin. (See Crystal Specifications on page 3). Crystal output pin. (See Crystal Specifications on page 3). Output frequency Selector pin. Output enable control pin. (See OE_CTRL Logic Levels on page 1). Do Not Connect Ground for analog circuitry. Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GND connection for output buffer circuitry. PECL or LVDS output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. Complementary PECL, LVDS output; Or single ended CMOS output. GND connection for output buffer circuitry. Output frequency Selector pin. Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
FREQUENCY SELECTION TABLE
SEL2
0 0 0 0 1 1 1 1
SEL1
0 0 1 1 0 0 1 1
SEL0
0 1 0 1 0 1 0 1
Selected Multiplier/Output Frequency
VCO Max* VCO Min* Reserved Reserved Fin x 2 Fin x 8 Fin x 16 Fin x 4
All SEL pads have internal pull-ups (default value is `1'). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink's `PhasorV Tuning Assistance' software to automatically calculate the optimum inductor values. In addition, the chart below could be used as a reference for quick inductor value selection. Use the special test modes "VCO Max" and "VCO Min" to determine the optimum inductor value. "VCO Max" represents the high end of the VCO range and "VCO Min" represents the low end of the VCO range. The output frequency in the "VCO Max" and "VCO Min" test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the "VCO Max" and "VCO Min" output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Shunt Capacitance Recommended ESR
SYMBOL
FXIN CL (xtal) C0 (xtal) RE
CONDITIONS
Parallel Fundamental Mode
MIN.
19
TYP.
17.7
MAX.
40 5 30
UNITS
MHz pF pF
AT cut
Note: Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS/CMOS PECL/LVDS 38MHzMIN.
TYP.
MAX.
65/45/30 90/70
UNITS
mA V % mA
@ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD - 1.3V (PECL)
2.25 45 45 45
50 50 50 50
3.63 55 55 55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
4. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY
106.25MHz 156.25MHz 212.5MHz 312.5MHz 622.08MHz 106.25MHz 156.25MHz 212.5MHz 312.5MHz 622.08MHz 106.25MHz 156.25MHz 212.5MHz 312.5MHz 622.08MHz
MIN.
TYP.
0.4 0.4 0.4 0.4 0.4 3 3 3 3 6 20 20 20 20 40
MAX.
0.5 0.5 0.5 0.5 0.5 5 5 5 5 8 30 30 30 30 50
UNITS
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
ps
Period jitter RMS
With capacitive decoupling between VDD and GND. Over 10,000 cycles.
ps
Period jitter Peak-toPeak
With capacitive decoupling between VDD and GND. Over 10,000 cycles.
ps
5. Phase Noise Specifications PARAMETERS FREQ.
106.25MHz Phase Noise relative to carrier (typical) 156.25MHz 212.5MHz 312.5MHz 622.08MHz @10Hz -66 -62 -62 -59 -49 @100Hz -96 -92 -92 -85 -84 @1kHz -122 -120 -118 -117 -111 @10kHz -132 -132 -126 -128 -120 @100kHz -126 -128 -120 -125 -118 @1M -144 -140 -140 -139 -128 @10M -150 -150 -150 -148 -138 dBc/Hz
UNITS
6. CMOS Electrical Characteristics PARAMETERS
Output drive current Output Clock Rise/Fall Time Output Clock Rise/Fall Time
SYMBOL
IOH IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load 20%-80% with 50 Load
MIN.
30 30
TYP.
MAX.
UNITS
mA mA
0.7 0.3
ns ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5
(Preliminary)
PL680-37/38/39
TYP.
355
38-640MHz Low Phase Noise XO
8. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
MAX.
454 50
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7
1.6 1.375 25 10 -8
Vout = VDD or GND VDD = 0V
9. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
SYMBOL
tr tf
CONDITIONS
RL = 100 CL = 10 pF (see figure)
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Levels Test Circuit
OUT
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
10. PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Low Voltage
SYMBOL
VOH VOL
CONDITIONS
RL = 50 to (VDD - 2V) (see figure)
MIN.
VDD - 1.025
MAX.
VDD - 1.620
UNITS
V V
11. PECL Switching Characteristics PARAMETERS
Clock Rise & Fall Times Clock Rise & Fall Times Clock Rise & Fall Times tr & tf
SYMBOL
FREQ.
<150MHz >150MHz <320MHz
CONDITIONS
MIN.
0.2 0.2 0.2
TYP.
0.5 0.4 0.3
MAX.
0.7 0.55 0.45
UNITS
ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
LAYOUT RECOMMENDATIONS
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL680 as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place a 0.01F~0.1F decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or `stripline', to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually `striplines' are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the `stripline' trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL680 layout.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
PACKAGE INFORMATION 16-PIN SSOP
16 PIN TSSOP ( mm )
Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H
D
A A1 e B C L
16-PIN 3x3 QFN
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 9
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PL680-3X X C L R
PART NUMBER R= TAPE & REEL NONE= TUBE L= GREEN PACKAGE NONE= REGULAR PACKAGE PACKAGE TYPE O=TSSOP Q= QFN 4x4 TEMPERATURE C=COMMERCIAL I=INDUSTRAL
Order Number
PL680-37OC PL680-37OC-R PL680-37OCL PL680-37OCL-R PL680-37QC PL680-37QC-R PL680-37QCL PL680-37QCL-R PL680-38OC PL680-38OC-R PL680-38OCL PL680-38OCL-R PL680-38QC PL680-38QC-R PL680-38QCL PL680-38QCL-R PL680-39OC PL680-39OC-R PL680-39OCL PL680-39OCL-R PL680-39QC PL680-39QC-R PL680-39QCL PL680-39QCL-R
Marking
P680-37OC P680-37OC P680-37OCL P680-37OCL P680-37QC P680-37QC P680-37QCL P680-37QCL P680-38OC P680-38OC P680-38OCL P680-38OCL P680-38QC P680-38QC P680-38QCL P680-38QCL P680-39OC P680-39OC P680-39OCL P680-39OCL P680-39QC P680-39QC P680-39QCL P680-39QCL
Marking
TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 10

▲Up To Search▲

Price & Availability of PL680-37

	To Download PL680-37 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .